Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation

Masashi KAMIYANAGI  Takuya IMAMOTO  Takeshi SASAKI  Hyoungjun NA  Tetsuo ENDOH  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.5   pp.760-766
Publication Date: 2011/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.760
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
current controlled-MCML,  MCML,  Vth fluctuation,  stability,  NMOS,  PMOS,  

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Summary: 
We have succeeded in fabricating 180 nm Current Controlled MOS Current Mode Logic (CC-MCML) and verified the stable circuit operation of 180 nm CC-MCML under threshold voltage fluctuations by measurement. The performance stability of the CC-MCML inverter under the fluctuations of threshold voltage of NMOS and PMOS is evaluated from the viewpoint of diminishing the bias offset voltage ΔVB. The ΔVB, that is defined as (base voltage of output waveform) - (base voltage of input waveform), is a key design parameter for differential circuit. It is shown that when the threshold voltage of NMOS fluctuates in the range of 0.53 V to 0.69 V, and threshold voltage of PMOS fluctuates in the range of -0.47 V to -0.67 V, the CC-MCML technique is able to suppress ΔVB within only 30 mV, where as the conventional MCML technique caused maximum ΔVB of 1.0 V. In this paper, it is verified for the first time that the fabricated CC-MCML is more tolerant against the fluctuations of threshold voltages than the conventional MCML.