Cascaded Time Difference Amplifier with Differential Logic Delay Cell

Shingo MANDAI  Toru NAKURA  Tetsuya IIZUKA  Makoto IKEDA  Kunihiro ASADA  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.4   pp.654-662
Publication Date: 2011/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.654
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
time-difference-amplifier,  TDA,  time amp,  

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We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.