For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A 500 MS/s 600 µW 300 µm2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process
Sarang KAZEMINIA Morteza MOUSAZADEH Kayrollah HADIDI Abdollah KHOEI
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
CMOS comparator, flash ADCs, kickback noise, high speed ADCs,
Full Text: PDF>>
This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500 MS/s comparison rate with 5 mv resolution for a 1.6 v peak-to-peak input signal range and 600 µw power consumption from a 3.3 v power supply by using TSMC model of 0.35 µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300 µm2.