A Duobinary Signaling for Asymmetric Multi-Chip Communication

Koichi YAMAGUCHI  Masayuki MIZUNO  

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.4    pp.619-626
Publication Date: 2011/04/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.619
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
partial response,  Duobinary signaling,  symbol-rate clock recovery,  oversampled equalizer,  

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Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.