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A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM
Tadayoshi ENOMOTO Nobuaki KOBAYASHI
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
SRAM, leakage power, “write” margin, “read” margin,
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We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11 V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17 µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0 V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138 MHz, which is 15% higher than that (120 MHz) of the conv. SRAM at VMM of 0.4 V. An area overhead was 0.81% that of the conv. SRAM.