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Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design
Norio SADACHIKA Shu MIMURA Akihiro YUMISAKI Kou JOHGUCHI Akihiro KAYA Mitiko MIURA-MATTAUSCH Hans Jurgen MATTAUSCH
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
circuit simulation, compact model, DFM, reliability,
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The long-standing problem of predicting circuit performance variations without a huge number of statistical investigations is demonstrated to be solvable by a surface-potential-based MOSFET model. Direct connection of model parameters to physical device parameters reflecting process variations and the reduced number of model parameters are the enabling key model properties. It has been proven that the surface-potential-based model HiSIM2 is capable of reproducing measured I-V and its derivatives' variations with those of device/process related model parameters. When used to predict 51-stage ring oscillator frequency variation including both inter- and intra-chip variation, it reproduces measurements with shortened simulation time.