A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis

Chizu MATSUMOTO
Yuichi HAMAMURA
Yoshiyuki TSUNODA
Hiroshi UOZAKI
Isao MIYAZAKI
Shiro KAMOHARA
Yoshiyuki KANEKO
Kenji KANAMITSU

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.3    pp.353-360
Publication Date: 2011/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defects,  failure analysis,  fail bit signature,  critical area analysis,  integrated circuit layout,  

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Summary: 
In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.