Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

Kazuyoshi TAKAGI
Yuki ITO
Masamitsu TANAKA
Naofumi TAKAGI

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.3    pp.288-295
Publication Date: 2011/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.288
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
single-flux-quantum circuit,  design methodology,  clock tree synthesis,  clock skew,  

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In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.