High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform

Ryosuke NAKAMOTO  Sakae SAKURABA  Alexandre MARTINS  Takeshi ONOMI  Shigeo SATO  Koji NAKAJIMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.3   pp.280-287
Publication Date: 2011/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.280
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
SFQ,  super-conductive circuits,  FFT,  multiplier,  adder,  

Full Text: PDF(2MB)>>
Buy this Article



Summary: 
We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.