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A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages
Jin-Fu LIN Soon-Jyh CHANG
Publication
IEICE TRANSACTIONS on Electronics
Vol.E94-C
No.1
pp.89-101 Publication Date: 2011/01/01 Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.89 Print ISSN: 0916-8516 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: analog-to-digital converter (ADC), data converter, correlated double sampling (CDS), time-interleaved, successive approximation (SA) ADC,
Full Text: PDF>>
Summary:
In this paper, two techniques for implementing a low-power pipelined analog-to-digital converter (ADC) are proposed. First, the time-interleaved correlated double sampling (CDS) technique is proposed to compensate the finite gain error of operational amplifiers in switched-capacitor circuits without a half-rate front-end sample-and-hold amplifier (SHA). Therefore, low-gain amplifiers and the SHA-less architecture can be used to effectively reduce power consumption of a pipelined ADC. Second, the back-end pipelined stages of a pipelined ADC are implemented using a low-power time-interleaved successive approximation (SA) ADC rather than operational amplifiers to further reduce the power consumption of the proposed pipelined ADC. A 9-bit, 100-MS/s hybrid pipelined-SA ADC is implemented in the TSMC 0.13 µm triple-well 1P8M CMOS process. The ADC achieves a spurious free dynamic range (SFDR) of 62.15 dB and a signal-to-noise distortion ratio (SNDR) of 50.85-dB for 2-MHz input frequency at a 100-MS/s sampling rate. The power consumption is 21.2 mW from a 1.2 V supply. The core area of the ADC is 1.6 mm2.
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