Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor

Shintaro NAKAMURA  Fujihiko MATSUMOTO  Pravit TONGPOON  Yasuaki NOGUCHI  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.1   pp.128-131
Publication Date: 2011/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.128
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
CMOS,  analog integrated circuits,  transconductors,  linear circuits,  low noise,  

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High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.