Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time

Woojun LEE  Kwangsoo KIM  Woo Young CHOI  

IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.1   pp.110-115
Publication Date: 2011/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.110
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
1T DRAM,  capacitorless DRAM,  low voltage,  data retention time,  

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A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.