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A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier
IEICE TRANSACTIONS on Electronics
Publication Date: 2011/12/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
time-to-digital converter (TDC), two-step TDC, phase-interpolator, time amplifier, all-digital phase-locked loop (ADPLL),
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In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm2. And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.