Low-Offset, Low-Power Latched Comparator Using Capacitive Averaging Technique

Kenichi OHHATA  Hiroki DATE  Mai ARITA  

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.12    pp.1889-1895
Publication Date: 2011/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1889
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
comparator,  offset voltage,  capacitive averaging,  analog-to-digital convertor,  

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We propose a capacitive averaging technique applied to a double-tail latched comparator without a preamplifier for an offset reduction technique. Capacitive averaging can be introduced by considering the first stage of the double-tail latched comparator as a capacitive loaded amplifier. This makes it possible to reduce the offset voltage while preventing an increase in power dissipation. A positive feedback technique is also used for the first stage, which maximizes the effectiveness of the capacitive averaging. The capacitive averaging mechanism and the relationship between the offset reduction and the linearity of the amplifier is discussed in detail. Simulation results for a 90-nm CMOS process show that the proposed technique can reduce the offset voltage by 1/3.5 (3 mV) at a power dissipation of only 45 µW.