Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving

Ning LI  Qinghong BU  Kota MATSUSHITA  Naoki TAKAYAMA  Shogo ITO  Kenichi OKADA  Akira MATSUZAWA  

IEICE TRANSACTIONS on Electronics   Vol.E94-C    No.12    pp.1881-1888
Publication Date: 2011/12/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1881
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Microwaves, Millimeter-Waves
low noise amplifier,  CMOS,  mm-wave integrated circuit,  60 GHz,  

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The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.