A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface

Ji-Hun EO  Sang-Hun KIM  Young-Chan JANG  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E94-C   No.11   pp.1798-1801
Publication Date: 2011/11/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E94.C.1798
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Electronic Circuits
Keyword: 
successive approximation,  analog-to-digital converter,  split-capacitor-based digital-to-analog converter,  time-domain comparator,  

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Summary: 
A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-µm 1-poly 6-metal CMOS process with a 1 V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 µW and 0.126 mm2, respectively. The FoM is 47 fJ/conversion-step.