IEICE Trans - Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors

Beomkyu SHIN  Hosung PARK  Jong-Seon NO  Habong CHUNG

Publication
IEICE TRANSACTIONS on Communications   Vol.E94-B   No.8   pp.2375-2377
Publication Date: 2011/08/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E94.B.2375
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Fundamental Theories for Communications
Keyword:
error floor,  log-likelihood ratio (LLR),  low-density parity-check (LDPC) codes,  sum-product algorithm,

Full Text: PDF(306.6KB)>>

Summary:
In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.