For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors
Beomkyu SHIN Hosung PARK Jong-Seon NO Habong CHUNG
IEICE TRANSACTIONS on Communications
Publication Date: 2011/08/01
Online ISSN: 1745-1345
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Fundamental Theories for Communications
error floor, log-likelihood ratio (LLR), low-density parity-check (LDPC) codes, sum-product algorithm,
Full Text: PDF(306.6KB)>>
In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.