Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes

Jianjun MU  Xiaopeng JIAO  Jianguang LIU  Rong SUN  

Publication
IEICE TRANSACTIONS on Communications   Vol.E94-B   No.6   pp.1725-1727
Publication Date: 2011/06/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E94.B.1725
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Fundamental Theories for Communications
Keyword: 
error floor,  low-density parity-check (LDPC) codes,  trapping sets,  

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Summary: 
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.