Processor Accelerator Customization through Data Flow Graph Exploration

Kang ZHAO  Jinian BIAN  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E94-A   No.7   pp.1540-1552
Publication Date: 2011/07/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E94.A.1540
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
algorithm,  instruction-set extension (ISE),  graph exploration,  

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To reduce the huge search space when customizing accelerators for the application specific instruction-set processor (ASIP), this paper proposes an automated customization method based on the data flow graph exploration. This method integrates the instruction identification and selection using an iterative improvement strategy, which uses a seed-growth algorithm to select the valid patterns that can bring higher performance enhancement. The search space is reduced by considering the performance factors during the identification stage. The experimental results indicate that the proposed method is feasible enough compared to the previous exhaustive algorithms.