For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Memory-Efficient Hardware Architecture for a Pulse Doppler Radar Vehicle Detector
Sang-Dong KIM Jong-Hun LEE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/05/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: Digital Signal Processing
pulse Doppler radar, FFT, memory-efficient hardware, Doppler shift,
Full Text: PDF>>
In this paper, we propose a memory-efficient structure for a pulse Doppler radar in order to reduce the hardware's complexity. The conventional pulse Doppler radar is computed by fast frequency transform (FFT) of all range cells in order to extract the velocity of targets. We observed that this method requires a huge amount of memory to perform the FFT processes for all of the range cells. Therefore, instead of detecting the velocity of all range cells, the proposed architecture extracts the velocity of the targets by using the cells related to the moving targets. According to our simulations and experiments, the detection performance of this proposed architecture is 93.5%, and the proposed structure can reduce the hardware's complexity by up to 66.2% compared with the conventional structure.