Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Juinn-Dar HUANG  Chia-I CHEN  Yen-Ting LIN  Wan-Ling HSU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E94-A   No.4   pp.1151-1155
Publication Date: 2011/04/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E94.A.1151
Print ISSN: 0916-8508
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
communication synthesis,  distributed register-file microarchitecture,  interconnect minimization,  resource binding,  scheduling,  

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In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.