For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems
Yong-Kyu KIM Chang-Seok CHOI Hanho LEE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/03/01
Online ISSN: 1745-1337
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
digital signal processing (DSP), FIR, filter, architecture, cubic spline, interpolation, digital TV (DTV),
Full Text: PDF(1.2MB)>>
This paper presents a low complexity partially folded architecture of transposed FIR filter and cubic B-spline interpolator for ATSC terrestrial broadcasting systems. By using the multiplexer, the proposed FIR filter and interpolator can provide high clock frequency and low hardware complexity. A binary representation method was used for designing the high order FIR filter. Also, in order to compensate the truncation error of FIR filter outputs, a fixed-point range detection method was used. The proposed partially folded architecture was designed and implemented with 90-nm CMOS technology that had a supply voltage of 1.1 V. The implementation results show that the proposed architectures have 12% and 16% less hardware complexity than the other kinds of architecture. Also, both the filter and the interpolator operate at a clock frequency of 200 MHz and 385 MHz, respectively.