Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications

Kisun JUNG  Hanho LEE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E94-A   No.11   pp.2376-2383
Publication Date: 2011/11/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E94.A.2376
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
DVB-T2,  FFT,  multi-mode,  scaling,  pipelined,  shared memory,  

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This paper presents a low-complexity multi-mode fast Fourier transform (FFT) processor for Digital Video Broadcasting-Terrestrial 2 (DVB-T2) systems. DVB-T2 operations need 1K/2K/4K/8K/16K/32K-point multiple mode FFT processors. The proposed architecture employs pipelined shared-memory architecture in which radix-2/22/23/24 FFT algorithms, multi-path delay commutator (MDC), and a novel data scaling approach are exploited. Based on this architecture, a novel low-cost data scaling unit is proposed to increase area efficiency, and an elaborate memory configuration scheme is designed to make single-port SRAM without degrading throughput rate. Also, new scheduling method of twiddle factor is proposed to reduce the area. The SQNR performance of 32K-point FFT mode is about 45.3 dB at 11-bit internal word length for 256QAM modulation. The proposed FFT processor has a lower hardware complexity and memory size compared to conventional FFT processors.