Setup Time, Hold Time and Clock-to-Q Delay Computation under Dynamic Supply Noise

Takaaki OKUMURA  Masanori HASHIMOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E94-A   No.10   pp.1948-1953
Publication Date: 2011/10/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E94.A.1948
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
power supply noise,  Flip-Flop,  setup time,  hold time,  timing analysis,  

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This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold times on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time, and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given voltage drop waveforms using an equivalent DC voltage approach. Experimental results show that the proposed procedure estimates setup time and clock-to-Q delay fluctuations well with 5% and 3% errors on average.