Nested Interrupt Analysis of Low Cost and High Performance Embedded Systems Using GSPN Framework

Cheng-Min LIN  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.9   pp.2509-2519
Publication Date: 2010/09/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.2509
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Software System
Keyword: 
performance evaluation,  interrupt service routine,  embedded systems,  generalized stochastic Petri nets,  

Full Text: PDF>>
Buy this Article




Summary: 
Interrupt service routines are a key technology for embedded systems. In this paper, we introduce the standard approach for using Generalized Stochastic Petri Nets (GSPNs) as a high-level model for generating CTMC Continuous-Time Markov Chains (CTMCs) and then use Markov Reward Models (MRMs) to compute the performance for embedded systems. This framework is employed to analyze two embedded controllers with low cost and high performance, ARM7 and Cortex-M3. Cortex-M3 is designed with a tail-chaining mechanism to improve the performance of ARM7 when a nested interrupt occurs on an embedded controller. The Platform Independent Petri net Editor 2 (PIPE2) tool is used to model and evaluate the controllers in terms of power consumption and interrupt overhead performance. Using numerical results, in spite of the power consumption or interrupt overhead, Cortex-M3 performs better than ARM7.