A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

Hiroshi IWATA  Satoshi OHTAKE  Hideo FUJIWARA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.7   pp.1857-1865
Publication Date: 2010/07/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.1857
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Information Network
Keyword: 
false path,  high level testing,  path mapping,  functional equivalence,  

Full Text: PDF(348.9KB)>>
Buy this Article




Summary: 
Information on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths.