High-Speed Low-Complexity Architecture for Reed-Solomon Decoders

Yung-Kuei LU  Ming-Der SHIEH  

IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.7   pp.1824-1831
Publication Date: 2010/07/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.1824
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
channel decoder,  modified Euclidean algorithm,  Reed-Solomon codes,  VLSI architectures,  

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This paper presents a high-speed, low-complexity VLSI architecture based on the modified Euclidean (ME) algorithm for Reed-Solomon decoders. The low-complexity feature of the proposed architecture is obtained by reformulating the error locator and error evaluator polynomials to remove redundant information in the ME algorithm proposed by Truong. This increases the hardware utilization of the processing elements used to solve the key equation and reduces hardware by 30.4%. The proposed architecture retains the high-speed feature of Truong's ME algorithm with a reduced latency, achieved by changing the initial settings of the design. Analytical results show that the proposed architecture has the smallest critical path delay, latency, and area-time complexity in comparison with similar studies. An example RS(255,239) decoder design, implemented using the TSMC 0.18 µm process, can reach a throughput rate of 3 Gbps at an operating frequency of 375 MHz and with a total gate count of 27,271.