For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Design and Optimization of Transparency-Based TAM for SoC Test
Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Information Network
SoC test, design for testability, TAM design, transparency, ILP,
Full Text: PDF(563.8KB)>>
We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.