Testable Critical Path Selection Considering Process Variation

Xiang FU
Huawei LI
Xiaowei LI

IEICE TRANSACTIONS on Information and Systems   Vol.E93-D    No.1    pp.59-67
Publication Date: 2010/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.59
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Dependable Computing
testable critical path selection,  process variation,  

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Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection.