IEICE Trans - High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

Kohei MIYASE  Xiaoqing WEN  Hiroshi FURUKAWA  Yuta YAMATO  Seiji KAJIHARA  Patrick GIRARD  Laung-Terng WANG  Mohammad TEHRANIPOOR

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E93-D   No.1   pp.2-9
Publication Date: 2010/01/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.2
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
Category:
Keyword:
power supply noise,  test relaxation,  X-filling,  clock-gating,  test compaction,

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Summary:
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.