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Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops
Hiroyuki YOTSUYANAGI Masayuki YAMAMOTO Masaki HASHIZUME
IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Online ISSN: 1745-1361
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Section on Test, Diagnosis and Verification of SOCs)
BIST-aided scan test, scan chain ordering, test data reduction, compatible flip-flops, test pattern generation,
Full Text: PDF(427.9KB)>>
In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work, we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting the bits in PRPG patterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method.