An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture

Shota ISHIHARA  Yoshiya KOMATSU  Masanori HARIYAMA  Michitaka KAMEYAMA  

IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.8   pp.1338-1348
Publication Date: 2010/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.1338
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
reconfigurable VLSI,  field-programmable VLSI,  LEDR (Level-Encoded Dual-Rail) encoding,  4-phase dual-rail encoding,  self-timed architecture,  

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This paper presents an asynchronous FPGA that combines 4-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. 4-phase dual-rail encoding is employed to achieve small area and low power for function units, while LEDR encoding is employed to achieve high throughput and low power for the data transfer using programmable interconnection resources. Area-efficient protocol converters and their control circuits are also proposed in transistor-level implementation. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process. Compared to the 4-phase-dual-rail-based FPGA, the throughput is increased by 69% with almost the same transistor count. Compared to the LEDR-based FPGA, the transistor count is reduced by 47% with almost the same throughput. In terms of power consumption, the proposed FPGA achieves the lowest power compared to the 4-phase-dual-rail-based and the LEDR-based FPGAs. Compared to the synchronous FPGA, the proposed FPGA has lower power consumption when the workload is below 35%.