A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology

Munehiko NAGATANI  Hideyuki NOSAKA  Shogo YAMANAKA  Kimikazu SANO  Koichi MURATA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.8   pp.1279-1285
Publication Date: 2010/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.1279
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2009)
Category: III-V High-Speed Devices and Circuits
Keyword: 
digital-to-analog converter (DAC),  R-2R,  current-steering,  InP HBT,  

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Summary: 
This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.