A 120-Gbit/s 1.27-W 520-mVpp 2:1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation

Yutaka ARAYASHIKI  Yukio OHKUBO  Taisuke MATSUMOTO  Yoshiaki AMANO  Akio TAKAGI  Yutaka MATSUOKA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.8   pp.1273-1278
Publication Date: 2010/08/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.1273
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2009)
Category: III-V High-Speed Devices and Circuits
Keyword: 
DHBT,  self-aligned,  ledge,  MUX,  broadband impedance matching,  module,  

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Summary: 
We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.