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Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates
Keivan NAVI Fazel SHARIFI Amir MOMENI Peiman KESHAVARZIAN
IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Full-Adder, nanotechnology, CNFET, CMOS,
Full Text: PDF(1.8MB)>>
In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.