Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

Keivan NAVI  Fazel SHARIFI  Amir MOMENI  Peiman KESHAVARZIAN  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.6   pp.932-934
Publication Date: 2010/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.932
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
Keyword: 
Full-Adder,  nanotechnology,  CNFET,  CMOS,  

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Summary: 
In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.