IEICE Trans - A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop

A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop

Hsin-Shu CHEN  Jyun-Cheng LIN

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.6   pp.855-860
Publication Date: 2010/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.855
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
delay-locked loop,  fast-lock,  low-power,  subranging,

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Summary:
A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm².