An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit

Yuji OKAZAKI  Takanori UNO  Hideki ASAI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.6   pp.827-834
Publication Date: 2010/06/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.827
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
EMI,  common-mode current,  optimization algorithm,  ECU,  parallel processing,  

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Summary: 
In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.