New Low-Voltage Low-Latency Mixed-Voltage I/O Buffer

Joung-Yeal KIM
Yong-Ki KIM
Sang-Keun HAN
Young-Hyun JUN
Chilgee LEE
Tae Hee HAN
Bai-Sun KONG

IEICE TRANSACTIONS on Electronics   Vol.E93-C    No.5    pp.709-711
Publication Date: 2010/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.709
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
mixed-voltage,  I/O buffer,  gate-oxide reliability,  leakage current,  hot-carrier degradation,  

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A new mixed-voltage I/O buffer for low-voltage low-latency operation is proposed in this paper. The proposed buffer adopts a novel delay-based timing-control scheme to efficiently avoid problems like gate-oxide stress and hot-carrier degradation. The proposed timing-control scheme also allows the buffer to have a lower latency for transmitting data by avoiding the use of timing-critical circuits like series-connected transmission gates (TGs) and triple-stacked transistors. The latency for receiving data at low supply voltage is also reduced by employing a variable stacked transistor gate-biasing scheme. Comparison results in an 80-nm CMOS process indicated that the proposed mixed-voltage I/O buffer improved up to 79.3% for receiving the external data and up to 23.8% for transmitting the internal data at a supply voltage of 1.2 V.