A Low Power Test Pattern Generator for BIST

Shaochong LEI  Feng LIANG  Zeye LIU  Xiaoying WANG  Zhen WANG  

IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.5   pp.696-702
Publication Date: 2010/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.696
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
built-in self-test (BIST),  power,  single input change (SIC),  fault coverage,  

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To tackle the increasing testing power during built-in self-test (BIST) operations, this paper proposes a new test pattern generator (TPG). With the proposed reconfigurable LFSR, the reconfigurable Johnson counter, the decompressor and the XOR gate network, the introduced TPG can produce the single input change (SIC) sequences with few repeated vectors. The proposed SIC sequences minimize switching activities of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can effectively save test power, and does not impose high impact on test length and hardware for the scan based design.