Multilevel Dual-Channel NAND Flash Memories with High Read and Program Verifying Speeds Utilizing Asymmetrically-Doped Channel Regions

Joung Woo LEE  Joo Hyung YOU  Sang Hyun JANG  Kae Dal KWACK  Tae Whan KIM  

IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.5   pp.654-657
Publication Date: 2010/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.654
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: Memory Devices
NAND flash memory,  multilevel dual-channel,  high-speed multilevel reading,  current sensing,  and high-speed program verifying,  

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The multilevel dual-channel (MLDC) not-AND (NAND) flash memories cell structures with asymmetrically-doped channel regions between the source and the drain were proposed to enhance read and program verifying speeds. The channel structure of the MLDC flash memories consisted of two different doping channel regions. The technical computer aided design simulation results showed that the designed MLDC NAND flash cell with asymmetrically-doped channel regions provided the high-speed multilevel reading with a wider current sensing margin and the high-speed program verifying due to the sensing of the discrete current levels. The proposed unique MLDC NAND flash memory device can be used to increase read and program verifying speed.