Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET

Tetsuo ENDOH  Koji SAKUI  Yukio YASUDA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.5   pp.557-562
Publication Date: 2010/05/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.557
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Emerging Devices
Keyword: 
vertical MOSFET,  3D structured device,  MOSFET,  LSI,  

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Summary: 
The excellent performance of the 10 nm gate Multi-Nano-Pillar type (M-) Vertical MOSFET has been numerically shown for the first time. It is made clear that the M-Vertical MOSFET, in comparison with the conventional Single Pillar type (S-) Vertical MOSFET, has achieved an increased driving current by more than 2 times, a nearly ideal S-factor, and a suppressed cutoff-leakage current by less than 1/60 by suppressing both the short channel effect and the DIBL effect. Moreover, mechanisms of these improvements of the M-Vertical MOSFET are made clear. From all of the above, it is shown that the M-Vertical MOSFET is a key device candidate for future high speed and low power LSI's in the sub-10 nm generation.