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Design and Implementation of 10-Gb/s Optical Receiver Analog Front-End in 0.13-µm CMOS Technology
Won-Seok OH Kang-Yeob PARK Kyu-Ho PARK Chang-Joon KIM Jong-Kook MOON
IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
optical receiver, pre amplifier, post amplifier, active feedback, negative impedance, CMOS,
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In this paper, a 10-Gb/s CMOS optical receiver analog front-end is designed and implemented in 0.13-µm CMOS technology. An optical receiver analog front-end includes a pre-amplifier and a post amplifier. To ensure 10-Gb/s operation, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, an advanced common-gate stage is exploited as the input stage of pre amplifier. To enhance the bandwidth without a passive inductor, a new post amplifier with active feedback and negative capacitance compensation techniques is proposed. A prototype chip has 98-dBΩ of trans-impedance gain (ZT), corresponding 40-dB input dynamic range (5-µA to 500-µA) and minimum allowable input current (5-µA). Also, the receiver achieves the bandwidth of 7.5-GHz for 0.25-pF photodiode parasitic capacitance, and the measured optical sensitivity equals -18-dBm for 10-12 bit error rate (BER).