Impact of Self-Heating in Wire Interconnection on Timing

Toshiki KANAMOTO  Takaaki OKUMURA  Katsuhiro FURUKAWA  Hiroshi TAKAFUJI  Atsushi KUROKAWA  Koutaro HACHIYA  Tsuyoshi SAKATA  Masakazu TANAKA  Hidenari NAKASHIMA  Hiroo MASUDA  Takashi SATO  Masanori HASHIMOTO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.388-392
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.388
Print ISSN: 0916-8516
Type of Manuscript: BRIEF PAPER
Category: 
Keyword: 
interconnect,  delay variation,  parasitic resistance,  thermal,  temperature,  self-heat,  SoC,  

Full Text: PDF>>
Buy this Article



Summary: 
This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32 nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heating cases. Experimental results show that the maximum wire temperature increase due to the self-heating appears in the case where the ratio of interconnect delay becomes largest compared to the driver delay. However, even in the most significant case which induces the maximum temperature rise of 11.0, the corresponding increase in the wire resistance is 1.99% and the resulting delay increase is only 1.15%, as for the assumed 32 nm process. A part of the impact reduction of wire self-heating on timing comes from the size-effect of nano-scale wires.