Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC

Yanfei CHEN  Xiaolei ZHU  Hirotaka TAMURA  Masaya KIBUNE  Yasumoto TOMITA  Takayuki HAMADA  Masato YOSHIOKA  Kiyoshi ISHIKAWA  Takeshi TAKAYAMA  Junji OGAWA  Sanroku TSUKAMOTO  Tadahiro KURODA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.295-302
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.295
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
ADC,  successive approximation,  split capacitor DAC,  comparator,  calibration,  

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Summary: 
Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03 mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.