Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm

Qingsheng HU  Hua-An ZHAO  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.279-287
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.279
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
input-queued switch,  scalable scheduling architecture,  packet scheduling,  

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Summary: 
To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64 64 FSSA using FSSA_DI algorithm is implemented by four Xilinx Vertex-4 FPGAs. Measurement results show that the data rates of our solution can be up to 800 Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.