A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder

Xianmin CHEN  Peilin LIU  Dajiang ZHOU  Jiayi ZHU  Xingguang PAN  Satoshi GOTO  

IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.3   pp.253-260
Publication Date: 2010/03/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.253
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
high performance,  low bandwidth,  motion compensation,  multi-standard,  2-D cache,  

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Motion compensation is widely used in many video coding standards. Due to its bandwidth requirement and complexity, motion compensation is one of the most challenging parts in the design of high definition video decoder. In this paper, we propose a high performance and low bandwidth motion compensation design, which supports H.264/AVC, MPEG-1/2 and Chinese AVS standards. We introduce a 2-Dimensional cache that can greatly reduce the external bandwidth requirement. Similarities among the 3 standards are also explored to reduce hardware cost. We also propose a block-pipelining strategy to conceal the long latency of external memory access. Experimental results show that our motion compensation design can reduce the bandwidth by 74% in average and it can real-time decode 1920x1088@30 fps video stream at 80 MHz.