A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme

Tadahiro KURODA

IEICE TRANSACTIONS on Electronics   Vol.E93-C    No.1    pp.120-127
Publication Date: 2010/01/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.120
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
wireless,  CMOS,  ultra-wideband,  transceiver,  quasi-millimeter-wave,  low-power,  

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A CMOS wireless transceiver operating in the 14-18 GHz range is proposed. The receiver uses direct conversion architecture for demodulation with a fast carrier and symbol timing recovery scheme. The transmitter uses a PLL and an up-conversion mixer to generate BPSK modulated signal. A ring oscillator is used in the PLL to make faster switching for burst transmission obtaining high speed low power operation. The transceiver operation has been verified by system simulation while the transmitter test-chip was fabricated in 65 nm CMOS technology and verified with measured results. The transmitter generates a bi-phase modulated signal with a center frequency of 16 GHz at a maximum data rate of 4 Gb/s and consumes 61 mW of power. To the best knowledge of authors, this is lowest power consumption among the reported transmitters that operate over 1 Gb/s range. The transceiver is proposed for a target communication distance of 10 cm.