For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation
Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM
IEICE TRANSACTIONS on Electronics
Publication Date: 2010/12/01
Online ISSN: 1745-1353
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
multiphase clock generation, error averaging, ring oscillator,
Full Text: PDF(1.2MB)>>
This paper presents a quantitative analysis and design methodology of resistor-based phase error averaging scheme for precise multiphase generation. Unlike the previously reported works stating that more averaging simply achieves better linearity, the proposed analysis leads to the existence of the optimum number of averaging contributions by including the effect of the signal transition time. The developed model shows a good agreement with a Monte-Carlo circuit simulation. A test PLL with a 32-phase two-dimensional ring VCO, implemented in a 0.18 µm CMOS, generates monotonous 32 phases with the best linearity performance, showing an INL of +0.27/-1.0 LSB and a DNL of +0.37/-0.27 LSB at 1.2 GHz, and an INL of +0.23/-1.57 LSB and a DNL of +0.44/-0.44 LSB at 1.6 GHz.