Performance and Power Modeling of On-Chip Bus System for a Complex SoC

Hyun LEE  Je-Hoon LEE  Kyoung-Rok CHO  

IEICE TRANSACTIONS on Electronics   Vol.E93-C   No.10   pp.1525-1535
Publication Date: 2010/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E93.C.1525
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
on-chip network,  performance modeling,  power estimation,  architecture level modeling,  system-on-chip,  

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This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.