A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection

Seongyong AHN  Hyejeong HONG  HyunJin KIM  Jin-Ho AHN  Dongmyong BAEK  Sungho KANG  

IEICE TRANSACTIONS on Communications   Vol.E93-B   No.9   pp.2440-2442
Publication Date: 2010/09/01
Online ISSN: 1745-1345
DOI: 10.1587/transcom.E93.B.2440
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Network Management/Operation
network intrusion detection system,  deep packet inspection,  pattern matching,  brute-force algorithm,  

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This paper proposes a new pattern matching architecture with multi-character processing for deep packet inspection. The proposed pattern matching architecture detects the start point of pattern matching from multi-character input using input text alignment. By eliminating duplicate hardware components using process element tree, hardware cost is greatly reduced in the proposed pattern matching architecture.